ChipAgents scores $21M to transform semiconductor design with agentic AI

Santa Barbara-based ChipAgents.ai today announced it raised $21M in early funding to fuel growth for its agentic artificial intelligence platform for chip design and verification.
IEEE

Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT

Abstract: This paper investigates the use of Large Language Models (LLMs) and natural language prompts to generate hardware description code, namely Verilog. Building on our prior work, we employ ...
GitHub

This repo contains a collection of Verilog +System Verilog +RTL +UVM Projects

There was an error while loading. Please reload this page. Welcome to the VLSI Design Verification Projects repository! This collection features various projects that ...
Semiconductor Engineering

Largest High-Quality Verilog Dataset for LLM Fine-Tuning (Univ. of Florida)

A new technical paper titled “VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation” was published by researchers at the University of Florida.
techxplore

Engineers create first AI model specialized for chip design language

Researchers at NYU Tandon School of Engineering have created VeriGen, the first specialized artificial intelligence model successfully trained to generate Verilog code, the programming language that ...
Semiconductor Engineering

Customizing An LLM Tailored Specifically For VHDL Code And Design Of High Performance Processors (IBM)

A new technical paper titled “Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors” was published by researchers at IBM. “The use of Large Language Models (LLMs) in ...
TechSpot

This techie created a GPU from scratch in under two weeks

In brief: Building your own graphics card is the kind of undertaking that most people wouldn't even dream of attempting. But for one enterprising engineer known as "adammaj" on X/Twitter, constructing ...
Scientific Research Publishing

Mano, M.M. and Ciletti, M.D. (2017) Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog. 6th Edition, Pearson, New York.

ABSTRACT: First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different ...
Electronic Design

Mixed-Signal Simulator Speaks Verilog-AMS

Designers today find themselves adding more and more analog and mixed-signal content to their creations. And at nanometer geometries and gigabit speeds, digital circuits begin to look more analog than ...